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745 IP
701
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process
UMC 65nm SP/RVT Low-K Logic process Powerlash Core Cell Library....
702
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library....
703
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process Low Power standard Cell Library....
704
0.118
Standard Cell PowerSlash(TM) Library IP, UMC 0.11um LL/FSG process
UMC 0.11um LL/FSG Logic process high density POWERSLASH Core Cell Library....
705
0.118
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process FSC0H_J POWERSLASHKit core Library....
706
0.118
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um LL/FSG process
UMC 0.13um LL FSG Logic process high density POWERSLASH Core Cell Library....
707
0.118
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um SP/FSG process
UMC 0.13um SP FSG Logic process high density POWERSLASH Core Cell Library....
708
0.118
Fujitsu 90mm LL-HS process MPCA core cell library [Minimum progeamming layer = M3/4/5 (MUST thin metal layers)]
Fujitsu 90mm LL-HS process MPCA core cell library [Minimum progeamming layer = M3/4/5 (MUST thin metal layers)]...
709
0.118
Fujitsu 90nm LL-UHS process MPCA M345 core cell library
Fujitsu 90nm LL-UHS process MPCA M345 core cell library...
710
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability
TSMC 152 G, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phenom...
711
0.0
7 track Extra Low Consumption standard cell library with Dual Voltage capability
TSMC 180 RFID, SESAME eLC is specifically designed to enable Dual Voltage operation (1.8 V +/- 10% 1.1 V +/- 10%) and to operate near threshold volt...
712
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V +/-10% / 1.1 V +/- 10%)
TSMC 180 BCD, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phen...
713
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)
TSMC 180 G, SESAME HD DV optimized for high density and low power, with characterizations taking into account physical phenomena linked to low voltage...
714
0.0
6 track High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME HD provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells....
715
0.0
6 track High Density standard cell library at TSMC 180 nm
Foundry Sponsored, TSMC 180 eLL, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-tr...
716
0.0
6 track High Density standard cell library at TSMC 180 nm
TSMC 180 uLL, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells and 1P3M ...
717
0.0
6 track High Density standard cell library at TSMC 180nm
TSMC 180 RF, SESAME HD optimized for high density and low power, RF models...
718
0.0
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLP, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-tra...
719
0.0
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLPeF, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-t...
720
0.0
9 track Near Threshold Voltage standard cell library at TSMC 55 nm
TSMC 55 uLPeF, SESAME NTV, an extreme low voltage library designed to operate down to the minimum data retention voltage allowing users to share the s...
721
0.0
8 track thick oxide standard cell library at TSMC 130 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 130 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
722
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
723
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 RF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
724
0.0
8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 90 LPeF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through th...
725
0.0
8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 90 LP, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
726
0.0
8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 90 uLL, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
727
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
Foundry Sponsored, TSMC 130 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi...
728
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
TSMC 130 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
729
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
730
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
731
0.0
6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
732
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 uLL, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest ...
733
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 LPeF, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
734
0.0
3DIO PHY IP for TSMC N5
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
735
0.0
CLICK - The universal solution of power gating for the whole SoC
CLICK is a power gating solution which create a ring of switches in order to ease�the integration of hard macro and provide automatic control of in-ru...
736
0.0
CLICK - The universal solution of power gating for the whole SoC
TSMC 180 eLL, CLICK, power gating cells to create a ring of switches in order to ease the integration of hard macro and provide automatic control of i...
737
0.0
CLICK - The universal solution of power gating for the whole SoC
TSMC 55 LP, CLICK, power gating cells to create a ring of switches in order to ease the integration of hard macro and provide automatic control of in-...
738
0.0
CLICK - The universal solution of power gating for the whole SoC
TSMC 55 LP, CLICK, power gating cells to create a ring of switches in order to ease the integration of hard macro and provide automatic control of in-...
739
0.0
CLICK - The universal solution of power gating for the whole SoC
TSMC 55nm uLPeF, CLICK, power gating cells to create a ring of switches in order to ease the integration of hard macro and provide automatic control o...
740
0.0
TSMC N3P 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
741
0.0
TSMC N3P Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
742
0.0
TSMC N3P Source Sync 3DIO PHY
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
743
0.0
TSMC N5 Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
744
0.0
Standard Cell Library, 0.45 V, 3nm, 7.5-Track
Silvaco’s low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance SoC designs. A...
745
0.0
Synthesizable 3DIO IP for Flexible Physical Implementation
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
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